A field programmable gate array (FPGA) is a large scale integration (LSI) constituting a digital circuit that supports the advance of a digital device and a network device. LSIs are generally divided into logical LSIs that execute signal processing, control, and the like in a device, and memories that accumulate data and programs. An FPGA is classified as a logical LSI thereamong.
In daily life, consumers rarely have the opportunity to see an FPGA. However, in a process in which a developer of an electronic device creates a prototype and increases the degree of completeness, an FPGA is almost always used. Recently, FPGAs have also been mounted in products to be purchased by consumers.
An FPGA has unique characteristics not found in other logical LSIs, such as an application specific integrated circuit (ASIC) that is a custom LSI, an application specific standard product (ASSP) that is a standard LSI, and a microprocessor. The unique characteristics are characteristics that an electronic circuit can be freely programmed. These characteristics keep up with development trends of electronic devices progressing in complication, scale, costs, and short product lifetime.
With the advent of microprocessors, a function of a device can be freely changed by rewriting software. However, even when a microprocessor is used, hardware cannot be changed in terms of, for example, a type of an arithmetic logic unit to be used and a structure of a memory. When an FPGA is used, a circuit structure that is hardware can be freely changed for the purpose of improved performance, low power consumption, or the like. Due to these characteristics, FPGAs are widely applied to devices including state-of-the-art industrial devices, such as base stations for mobile phones and semiconductor manufacturing apparatuses, to household devices, such as digital home appliances and mobile devices.
A variety of technologies related to such circumstances are known (for example, see Patent Documents 1 to 3).
For example, Patent Document 1 discloses an information processing system which includes a central processing unit (CPU), a memory, a bus under control of the CPU and the memory, and a configuration control means arranged on the bus and performing configuration control of an FPGA. More specifically, this information processing system includes a bus switch for disconnecting the FPGA from the bus from start to end of the configuration control. Thus, the information processing system provides an advantageous effect that, when the FPGA subjected to configuration control accommodates a system bus and the like, the FPGA is disconnected from the bus using a reset signal as an enable signal for the bus switch, thereby realizing continuous availability of the system.
Further, for example, Patent Document 2 discloses a method for guaranteeing startup of a programmable logic circuit in which one of logic circuit data stored in a first memory and logic circuit data stored in a second memory is read and the configuration is performed to determine the structure of the logic circuit at the time of startup after power-on. More specifically, in the method for guaranteeing startup of a programmable logic circuit, at the time of startup of the programmable logic circuit, after the programmable logic circuit performs initialization, logic circuit data stored in the first memory is read, the configuration is performed, an elapsed time of the configuration in the programmable logic circuit until the configuration is completed is monitored, it is determined that the first memory is abnormal if the elapsed time exceeds a set time, and an abnormality notification signal is generated. Then, in the method for guaranteeing startup of a programmable logic circuit, when the abnormality notification signal is received, the memory is switched from the first memory to the second memory, and the configuration is performed on the programmable logic circuit again using logic circuit data stored in the second memory. In this way, with this method for guaranteeing startup of a programmable logic circuit is used, the memory is automatically switched to the second memory and the configuration of the programmable logic circuit can be executed even if the first memory for configuration fails.
Further, for example, Patent Document 3 discloses a configuration technique in which after power-on, an FPGA reads circuit information stored in a first configuration read only memory (ROM) and a second configuration ROM and the FPGA is subjected to configuration. More specifically, in this configuration technique, first, the FPGA starts the configuration from the first configuration ROM. Then, in this configuration technique, when the configuration is being performed from the first configuration ROM, if a configuration error detection signal is output from the FPGA, a configuration path is switched to the second configuration ROM, and the configuration starts from the second configuration ROM. Thus, using this configuration technique, it is possible to guarantee the startup of the FPGA while shortening time from power-on to startup of the FPGA.